|
13:00
|
Introduction and organization issues
- Sr.
Enrique Sanchis
(Dep. Electronic Engineering - Universidad de Valencia)
()
|
|
13:10
|
Status and plans for mezzanine board
- Sr.
Fernando Carrió
(Dep. Electronic Engineering - Universidad de Valencia)
()
|
|
13:30
|
Status and plans for Xilinx development
- Sr.
Pablo Moreno
(IFIC - Universidad de Valencia)
()
|
|
13:50
|
LIB collaboration
- Sr.
Alberto Valero
(IFIC- Universidad de Valencia)
()
|
|
14:00
|
AOB
- Sr.
Enrique Sanchis
(Dep. Electronic Engineering - Universidad de Valencia)
()
|