2-9 julio 2014
Valencia, Spain
Europe/Madrid timezone

Readout electronics for the Silicon micro-strip detector of the ILD concept

No programado
20m
Valencia, Spain

Valencia, Spain

Poster Detector RD and Performance

Ponente

Dr. Oscar Alonso (Universitat de Barcelona)

Descripción

Si-strips are the baseline for the forward tracker detector (FTD) of the International Linear Detector (ILD). The main element of the front-end (FE) electronics is a multi-channel System-on-Chip (SoC) for self-triggered detection and processing of low level charge signals. The architecture used in this chip is very similar to the typical structure of a silicon strip readout system presented in previous works (ABCD3T, APV25, Beetle chip, KPiX or SiTRK). For the FE there are special considerations to be taken, given that the FE resides inside the detector. It must be designed to meet two conflicting requirements: low power and low noise. Low power FE electronics is a necessity to avoid cooling systems in the detector. If the FE is not designed with the necessary low power dissipation, the generated heat will become unmanageable. To achieve these goals the appropriate choice of which semiconductor technology to use must be done. Deep and ultra-deep submicron CMOS has been the technology of choice for low power applications in the last decade, at least in the digital field of electronics. These technologies also assure the necessary radiation hardness, which is not critical in ILC. Moreover, all modules are designed with power-off capabilities to adapt the operation to the ILC structure and pulsed power mode of operation. This mode together with the low power of each module will satisfy the power constraints for this chip below 700uW/channel in continuous (not pulsed) operation. A reduction of a factor 50-200 can be expected with pulsed operation. To reduce the noise a pre-amplifier and a shaping amplifier are added at the beginning of each channel. In this talk we discuss the work done in the readout electronics, starting from the modelling of one channel in Verilog-AMS, noise estimations and finishing with the design of the analog circuits designed in 65nm CMOS technology from TSMC.

Autor primario

Dr. Oscar Alonso (Universitat de Barcelona)

Coautores

Dr. Angel Dieguez (University of Barcelona) Dr. Eva Vilella Figueras (Universitat de Barcelona)

Materiales de la presentación

Ponencia

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