Moderadores
Electronics (ASIC, DAQ, Trigger, powering) WG
- Diego Real Mañez (IFIC)
- Fernando Arteche (Instituto Tecnológico de Aragón)
- Santiago Folgueras (Universidad de Oviedo)
The ECFA DRD7 (Electronics and On-Detector Processing) collaboration is dedicated to the advancement of technologies for high-performance electronic systems for future physics detectors. The collaboration includes R&D projects in six areas (organized as Working Groups). One of them is focused on power efficiency (WG 7.1) and other in advanced 4D and 5D techniques (WG 7.3). Within DRD7...
Considering the upcoming HL-LHC, the Phase-2 CMS upgrade is set to revamp the trigger and data acquisition system. Upgrading the readout electronics to handle a maximum L1 accept rate of 750 kHz and a latency of 12.5 µs.The muon trigger is a multi-layered system designed to reconstruct and measure muon momenta by analyzing data from muon chambers using advanced pattern recognition algorithms...
The VEGA group at IFIC is leading the research and development of the acquisition electronics for the KM3NeT neutrino telescope. This contribution provides an overview of the acquisition electronics employed in KM3NeT, its upgrades and current developments. It showcases the already developed 1-ns Time to Digital Converters (TDCs) and discusses ongoing progress in resolution enhancement and...
Abstract: Enhancing Data Processing in the CMS Trigger System for HL-LHC with HLS
In the context of the HL-LHC upgrades at the CMS experiment, handling the immense data volume efficiently is pivotal. This paper discusses the integration of High-Level Synthesis (HLS) for hardware acceleration, a key innovation in processing High Energy Physics (HEP) data. HLS effectively bridges the complex...
Instrumentation for future colliders will require electronics that works under harsh conditions which includes levels of radiation that varies depending on the collider proposal but also on the actual detector configuration. Having the possibility to instrument a detector with reconfigurable hardware opens many possibilities for versatile designs and for functionality modification after...
This work presents the analog design of a 4-channel ASIC developed in a 65 nm CMOS technology specifically designed to be included in the Front-End Board (FEB) of the LHCb Upgrade II Calorimeter. It is intended for the continuous readout of Photomultiplier Tubes (PMTs), achieving an energy measurement of the particle collisions with a resolution of 12 bit/channel and a power consumption of ~...
Improving timing resolution will be an important challenge for the next generation of particle physics detectors. One of the intrinsic aspects to achieve when using TDCs (Time to Digital Converters) is the quality and the low jitter of the clock. Thus, clock distribution becomes critical to ensure an optimal time measurement and this is usually done through a chain of FPGAs connected via...
Current Imaging Atmospheric Cherenkov Telescopes (IACT) use combined analog and digital electronics for their trigger systems, implementing simple but fast algorithms. Such trigger techniques are used due to the extremely high data rates and strict timing requirements. In recent years, in the context of a new camera design for the Large-Sized Telescopes (LSTs) of the Cherenkov Telescope Array...
The High-Luminosity LHC (HL-LHC) project is planned as a major upgrade to maintain and expand the LHC’s discovery potential. As part of this upgrade, the ATLAS experiment has developed a comprehensive roadmap for upgrades, including the installation of new detector components and advancements in data acquisition and processing systems. A critical aspect of these upgrades involves the complete...
