Ponente
Dr.
Yusheng Wu
(University of Michigan (United States))
Descripción
To maximize the physics reach for the high energy and high luminosity LHC, the ATLAS collaboration plans to build and install a new small wheel (nSW) detector with eight layers of MicroMegas (MM) detector and eight layers of small-strip Thin Gap Chambers (sTGC) to improve the Level-1 muon triggering as well as the offline muon precision tracking. For the sTGC trigger path, both pad and strip detector signals will be first amplified, shaped, discriminated and digitizied. A trigger data serializer (TDS) ASIC chip is then needed to prepare trigger data for many input channels with the additional task of serializing data to the circuitry on the rim of the nSW detector. The large number of input channels (128 differential input channels), short time available to prepare and transmit trigger data (<100 ns), high speed output data rate (5 Gbps), harsh radiation environment (about 300 kRad), and low power consumption (<1 W), impose great challenges for the design of this ASIC chip using the IBM 130 nm CMOS process. We will present our design and test results of the TDS ASIC chip.
Autor primario
Junjie Zhu
(University of Michigan)
Ponencia
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