Ponente
Descripción
The High-Luminosity LHC (HL-LHC) project is planned as a major upgrade to maintain and expand the LHC’s discovery potential. As part of this upgrade, the ATLAS experiment has developed a comprehensive roadmap for upgrades, including the installation of new detector components and advancements in data acquisition and processing systems. A critical aspect of these upgrades involves the complete replacement of the readout electronics of the ATLAS central Tile hadronic calorimeter. This upgrade aims to enhance the system's capacity to handle higher data rates and improve its resistance to radiation. Through these comprehensive improvements, the ATLAS experiment aims to meet the requirements and seize the opportunities presented by the HL-LHC era.
This contribution presents the architecture and design of the TilePPr (Tile PreProcessor) system, which serves as a crucial interface between the on-detector electronics and the central Trigger, Detector Control and Data Acquisition systems of the ATLAS experiment. The TilePPr module is based on the Advanced Telecommunications Computing Architecture (ATCA) and incorporates high-speed optical links, communication interfaces, and data processing capabilities. Through a series of certification tests, the module has demonstrated its compliance with industry standards and functional requirements, confirming its suitability for seamless integration into the ATLAS experiment during the HL-LHC phase.
Moreover, a key component of this upgrade is the development and optimisation of robust signal reconstruction algorithms tailored to the challenging high-pileup conditions expected during HL-LHC operation. The objective is to identify an algorithm that not only meets the stringent latency requirements but also integrates effectively with the ATLAS trigger system, ensuring synchronous, high-precision data processing in real time. These improvements in reconstruction will enable efficient handling of HL-LHC's increased data rates with high precision.
