Ponente
Descripción
Current Imaging Atmospheric Cherenkov Telescopes (IACT) use combined analog and digital electronics for their trigger systems, implementing simple but fast algorithms. Such trigger techniques are used due to the extremely high data rates and strict timing requirements. In recent years, in the context of a new camera design for the Large Size Telescopes (LSTs) of the Cherenkov Telescope Array (CTA) based on Silicon PhotoMultipliers (SiPM), a new fully digital trigger system incorporating Machine Learning (ML) algorithms is being developed. The main concept is to implement those algorithms in Field Programmable Gate Arrays (FPGAs) to increase the sensitivity and efficiency of the real-time decision-making while being able to fulfill timing constraints. The project is full of challenges, such as complex Printed Circuit Board (PCB) design, managing very wide bandwidths, complex FPGA logic design, and translating high level ML models to FPGA synthesizable code. We are currently developing all the elements of such a ML-based IACT trigger system, starting with a PCB prototype to test multi-gigabit optical transceivers and using development boards as an algorithmic testbench.
Abstract
Current Imaging Atmospheric Cherenkov Telescopes (IACT) use combined analog and digital electronics for their trigger systems, implementing simple but fast algorithms. Such trigger techniques are used due to the extremely high data rates and strict timing requirements. In recent years, in the context of a new camera design for the Large Size Telescopes (LSTs) of the Cherenkov Telescope Array (CTA) based on Silicon PhotoMultipliers (SiPM), a new fully digital trigger system incorporating Machine Learning (ML) algorithms is being developed. The main concept is to implement those algorithms in Field Programmable Gate Arrays (FPGAs) to increase the sensitivity and efficiency of the real-time decision-making while being able to fulfill timing constraints. The project is full of challenges, such as complex Printed Circuit Board (PCB) design, managing very wide bandwidths, complex FPGA logic design, and translating high level ML models to FPGA synthesizable code. We are currently developing all the elements of such a ML-based IACT trigger system, starting with a PCB prototype to test multi-gigabit optical transceivers and using development boards as an algorithmic testbench.
