Ponente
Descripción
This work presents the analog design of a 4-channel ASIC developed in a 65 nm CMOS technology specifically designed to be included in the Front-End Board (FEB) of the LHCb Upgrade II Calorimeter. It is intended for the continuous readout of Photomultiplier Tubes (PMTs), achieving an energy measurement of the particle collisions with a resolution of 12 bit/channel and a power consumption of ~ 50 mW/channel. The radiation levels inside the detector and the necessity of matching the analog and digital blocks in the FEB bind the design to the TSMC65 technology.
This technology is powered by a reduced voltage supply of 1.2V, which leads to a very limited dynamic range (DR) and lower Signal-to-Noise Ratio (SNR) than the one achieved in the Calorimeter Upgrade I. In order to fulfill the 12 bits resolution specification, the ASIC includes two gain paths: Low-Gain (LG), using an input preamplifier with unity gain, and a High-Gain (HG) path that increases the resolution for low-amplitude input pulses to 11+1 bits/channel. Both paths are, in turn, divided into two time-interleaved subchannels that allow the signal integration to reset between input events (occurring every 25 ns) and remove the dead time, preventing information losses.
The design is based on the experience of ICECAL ASIC already installed the current detector, including: (1) Rail-to-rail (RTR) input and output swings to cover the maximum DR available from the reduced voltage supply; (2) fully-differential operation to improve the common noise rejection due to the switched nature of the channel; (3) individual generation of integration clocks using a Phase Locked Loop (PLL) with a 1 ns resolution to calibrate channel to channel variations due to the different signal paths of the PMTs; (4) a fully-differential driver with a capacitance drive capability up to 10 pF to output the analog signal to be digitized off-chip with an external 12 bits Analog-To-Digital Converter (ADC).
