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SUMMARY:Developments for the ATLAS Tile Hadronic Calorimeter at the LHC
DTSTART;VALUE=DATE-TIME:20230207T110000Z
DTEND;VALUE=DATE-TIME:20230207T111500Z
DTSTAMP;VALUE=DATE-TIME:20260312T192846Z
UID:indico-contribution-20051@indico.ific.uv.es
DESCRIPTION:Speakers: Alberto Valero ()\nTileCal is the hadron calorimeter
  covering the central region of the ATLAS experiment at the Large Hadron C
 ollider. It is a sampling detector made of iron as absorber and scintillat
 or as active material. The light produced by charged particles crossing th
 e scintillator tiles is collected by photomultiplier tubes (PMTs). The PMT
  signals are digitized synchronously with the LHC clock\, and the samples 
 corresponding to events selected by the Level 1 trigger system are transmi
 tted to the Read-Out Drivers (RODs) located in the back-end system at a ma
 ximum sustained rate of 100 kHz. The ROD is the core element of the back-e
 nd electronics\, and it represents the interface between the front-end ele
 ctronics and the ATLAS overall Data AcQuisition (DAQ) system. It is respon
 sible for energy and time reconstruction\, trigger and data synchronizatio
 n\, busy handling\, data integrity checking and lossless data compression.
  The IFIC-TileCal group was responsible for the design\, production\, inst
 allation and now the maintenance of the ROD system until the end of Run 3.
 \n\n\n\nThe High-Luminosity Large Hadron Collider (HL-LHC) experiments wil
 l operate at unprecedented values of peak luminosity and levels of pileup.
  The ATLAS trigger and readout architecture has been redefined. TileCal wi
 ll read out the PMTs signals for every bunch crossing before any trigger s
 election is applied\, which implies a total bandwidth of 40 Tbps. These da
 ta will be processed by the PreProcessors (PPr) located in the off-detecto
 r electronics. The PPr modules will implement the interface with the fully
  digital Level 0 trigger and ATLAS overall DAQ and detector control system
 s. The TilePPr is a modular ATCA system composed of a custom ATCA Carrier 
 board equipped with 4 Compact Processing Modules (CPM) and several mezzani
 ne cards. The IFIC-TileCal group is responsible for the hardware and firmw
 are designs\, production\, installation and maintenance of the PPr modules
 .\n\nThis presentation will provide an overview of the current and future 
 systems for the HL-LHC\, including a thorough explanation of the ongoing h
 ardware and firmware developments within the IFIC-TileCal group.\n\nhttps:
 //indico.ific.uv.es/event/6924/contributions/20051/
LOCATION:Universe
URL:https://indico.ific.uv.es/event/6924/contributions/20051/
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